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datasheet 2 output pcie gen1 -2-3 synthesizer IDT5V41315 idt? 2 output pcie gen1-2-3 synthesizer 1 IDT5V41315 may 8, 2017 recommended applications pcie gen1-2-3 synthesizer for common and srns-clocked systems general description the IDT5V41315 is a pcie gen1-2-3 clock synthesizer suitable for use in both common-clocked and separate reference clock with no spread (srns) timing architectures. the IDT5V41315 uses a 25mhz input to generate 4 different output frequencies. the output frequency is selectab le via select pins. output features ? 2 - 0.7v current mode differential hcsl output pairs features/benefits ? 16-pin tssop or vfqfpn package; small board footprint ? outputs can be terminated to lvds; can drive a wider variety of devices ? oe control pin; greater system power management ? industrial temperature range available; supports demanding embedded applications key specifications ? cycle-to-cycle jitter: 80ps ? output-to-output skew: <50 ps ? pcie gen2 phase jitter: <3.0ps rms (common clock) ? pcie gen3 phase jitter: <1.0ps rms (common clock) ? low phase noise: 12khz to 20mhz <6ps rms block diagram phase lock loop clock buffer/ crystal oscillator vdd gnd x1/iclk x2 25 mhz crystal or clock control logic s1:s0 2 clk0 clk0 rr(iref) clk1 clk1 2 2 oe optional tuning crystal capacitors
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 2 IDT5V41315 may 8, 2017 pin assignments output select table 1 (mhz) pin descriptions 1 2 3 x2 4 s1 5 6 clk0 7 8 clk0 gndoda vddxd oe nc 16 x1/iclk nc clk1 vddoda 15 14 13 12 11 10 9 16-pin (173 mil) tssop gndxd s0 iref clk1 s0 vddxd clk0 clk0# 16 15 14 13 s1 1 12 gndoda nc 2 11 vddoda x1 / cl k 3 1 0 c l k 1 x2 4 9 cl k 1 # 5678 oe gndxd nc iref 16-pin vfqfpn 5v41315 s1 s0 clk(1:0), clk(1:0) 00 25m 0 1 100m 1 0 125m 1 1 200m vfqfpn pin number tssop pin number pin name pin type pin description 16 1 s0 input select pin 0. see table1. internal pull-up resistor. 1 2 s1 input select pin 1. see table 1. internal pull-up resistor. 2 3 nc -- no connect. 3 4 x1/iclk input crystal or clock input. connect to a 25 mhz crystal or single ended clock. 4 5 x2 output crystal connection. leave unconnected for clock input. 5 6 oe input output enable. tri-states outputs and device is not shut down. internal pull-up resistor. 6 7 gndxd power connect to ground. 7 8 nc -- no connect. 8 9 iref output precision resistor attached to this pin is connected to the internal current reference, typically 475 ohm. 9 10 clk1 output hcsl complementary clock output 1. 10 11 clk1 output hcsl true clock output 1. 11 12 vddoda power connect to voltage supply +3.3 v for output driver and analog circuits 12 13 gndoda power connect to ground. 13 14 clk0 output hcsl complementary clock output 0. 14 15 clk0 output hcsl true clock output 0. 15 16 vddxd power connect to voltage supply +3.3 v for crystal oscillator and digital circuit.
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 3 IDT5V41315 may 8, 2017 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the IDT5V41315. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended op erating temper ature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , t a = t ambient 1. single edge is monotonic when transitioning through region. 2. inputs with pull-ups/-downs are not included. item rating supply voltage, vddxd, vddoda 4.6 v all inputs and outputs -0.5 v to vdd+0.5 v storage temperature -65 to +150 ? c junction temperature 125 ? c soldering temperature 260 ? c esd protection (input) 2000 v min. (hbm) parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.3 3.465 v ambient operating temperature t ambient industrial temperature range -40 +25 +85 c input high voltage 1 v ih s0, s1, oe, iclk 2.2 vdd +0.3 v input low voltage 1 v il s0, s1, oe, iclk vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 ? a operating supply current @100 mhz i dd r s =33 ??? r p =50 ? , c l =2 pf 63 85 ma i ddoe oe =low 42 50 ma input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf x1, x2 capacitance c inx 5pf pin inductance l pin 5nh output impedance z o clk outputs 3.0 k ? pull-up resistor r pu s0, s1, oe 100 k ?
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 4 IDT5V41315 may 8, 2017 ac electrical characterist ics - clk0/clk1, clk0/clk1 unless stated otherwis e, vdd=3.3 v 5%, t a = t ambient note 1: test setup is r s =33 ??? r p =50 ? with c l =2 pf, rr = 475 ? (1%). note 2: measurement taken from a single-ended waveform. note 3: measurement taken from a differential waveform. note 4: measured at the crossing point where instantaneous voltages of both clk and clk are equal. note 5: clk pins are tri-stated when oe is low asserted. clk is driven differential when oe is high. electrical characteristics - di fferential phase jitter parameters parameter symbol conditions min. typ. max. units input frequency 25 mhz output frequency hcsl termination 25 200 mhz lvds termination 25 100 mhz output high voltage 1,2 v oh hcsl 850 mv output low voltage 1,2 v ol hcsl -150 mv crossing point voltage 1,2 absolute 250 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 80 ps frequency synthesis error all outputs 0 ppm rise time 1,3 t or 150mv 1 4 v/ns fall time 1,3 t of 150mv 1 4 v/ns rise/fall time variation 1,2 125 ps output to output skew 50 ps duty cycle 1,3 45 55 % output enable time 5 all outputs 50 100 ns output disable time 5 all outputs 50 100 ns stabilization time t stable from power-up vdd=3.3 v 1.8 ms parameter symbol conditions min typ max units notes t jp haseg1 pcie gen 1 32 86 ps (p-p) 1,2,3 t jphaseg2lo pcie gen 2 10khz < f < 1.5mhz 0.7 3 ps (rms) 1,2,3 t jphaseg2high pcie gen 2 1.5mhz < f < nyquist (50mhz) 2.3 3.1 ps (rms) 1,2,3 t jphaseg3 pcie gen 3 0.6 1 ps (rms) 1,2,3 t jphase12k20m 12khz-20mhz n/a ps (rms) 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. t a = t ambient , supply voltage vdd = 3.3 v +/-5% 2 see http://www.pcisig.com for complete specs 3 applies to 100mhz jitter, phase
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 5 IDT5V41315 may 8, 2017 applications information external components a minimum number of external components are required for proper operation. decoupling capacitors decoupling capacitors of 0.01 ?? f should be connected between each vdd pin and the ground plane, as close to the vdd pin as possible. do not share ground vias between components. route power from power source through the capacitor pad and then into ics pin. crystal a 25 mhz fundamental mode parallel resonant crystal should be used. this crystal must have less than 300 ppm of error across temperature in order for the IDT5V41315 to meet pci express specifications. crystal capacitors crystal capacitors are connected from pins x1 to ground and x2 to ground to optimize the accuracy of the output frequency. c l = crystal?s load capacitance in pf crystal capacitors (pf) = (c l - 8) * 2 for example, for a crystal with a 16 pf load cap, each external crystal cap would be 16 pf. (16-8)*2=16. current source (iref) reference resistor - r r if board target trace impedance (z) is 50 ? , then r r = 475 ? (1%), providing iref of 2.32 ma. the output current (i oh ) is equal to 6*iref. output termination the pci-express differential clock outputs of the IDT5V41315 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the IDT5V41315 can also be configured for lvds compatible voltage levels. see the lvds compatible layout guidelines section. output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the IDT5V41315.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5 ?
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 6 IDT5V41315 may 8, 2017 layout guidelines common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 7 IDT5V41315 may 8, 2017 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 8 IDT5V41315 may 8, 2017 typical pci-express (hcsl) waveform typical lvds waveform 0.175 v 0.525 v 0.175 v 0.525 v t or t of 500 ps 500 ps 700 mv 0 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 9 IDT5V41315 may 8, 2017 thermal characteristics (16-tssop) thermal characteristics (16-vfqfpn) marking diagrams notes: 1. ?xxx? denotes lot number. 2. ?#? denotes die revision. 3. ?yyww? or ?yww? denotes date code 4. ?$? denotes assembly location. 5. ?g? after the two-letter package code designates rohs compliant package. 6. ?i? at the end of part number indicates industrial temperature range. 7. bottom marking: country of origin if not usa (tssop package only). parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 78 ? c/w ? ja 1 m/s air flow 70 ? c/w ? ja 3 m/s air flow 68 ? c/w thermal resistance junction to case ? jc 37 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 63.2 ? c/w ? ja 1 m/s air flow 55.9 ? c/w ? ja 3 m/s air flow 51.4 ? c/w thermal resistance junction to case ? jc 65.8 ? c/w 1 8 9 16 idt5v413 15pggi #yyww$ xxx yww$ 315i
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 10 IDT5V41315 may 8, 2017 package outline and dimensions (3 x 3 mm 16-vfqfpn)
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 11 IDT5V41315 may 8, 2017 package outline and dimensions (3 x 3 mm 16-vfqfpn), cont.
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 12 IDT5V41315 may 8, 2017 package outline and dimensions (16-tssop, 4.4 mm body)
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 13 IDT5V41315 may 8, 2017 package outline and dimensions (16-tssop, 4.4 mm body), cont.
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 14 IDT5V41315 may 8, 2017 package outline and dimensions (16-tssop, 4.4 mm body), cont.
IDT5V41315 2 output pcie gen1-2-3 synthesizer idt? 2 output pcie gen1-2-3 synthesizer 15 IDT5V41315 may 8, 2017 ordering information ?g? after the two-letter package code denote s pb-free configuratio n, rohs compliant. revision history part / order number marking shipping packaging package temperature 5v41315pggi see page 9 tubes 16-pin tssop -40 to +85 ? c 5v41315pggi8 tape and reel 16-pin tssop -40 to +85 ? c 5v41315nlgi trays 16-pin vfqfpn -40 to +85 ? c 5v41315nlgi8 tape and reel 16-pin vfqfpn -40 to +85 ? c rev. date originator description of change a 10/24/12 j. chao initial release?preliminary b 03/20/13 r. wade 1. updated general description verbiage. 2. added 16-pin vfqfpn package and pinout 3. updated pin descriptions for both t ssop and vfqfpn 4. minor updates to ac/dc char tables. 5. updated differential phase jitter parame ters table; removed typical specs, added ?tjphase12k20m? parameter. 6. added 16-pin vfqfpn package drawing/dimens ions, thermal characteristics, marking diagram, and ordering information b 07/30/13 j. chao updated device top-side marking on vfqfpn package; removed ?g?. c 09/20/13 rdw changed rise/fall times to differential slew rates. d 06/01/15 ih added typical values to differential phase jitter table. e 05/08/17 c.p. updated package outline drawings and legal disclaimer.
disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idt?s sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any part icular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in su ch a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of co mmon terms, visit www.idt.com/go/glossary. integrated device technology, inc.. all rights reserved. corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 www.idt.com/go/sales for tech support www.idt.com/go/support innovate with idt and accelerate your future netw orks. contact: www.idt.com IDT5V41315 2 output pcie gen1-2-3 synthesizer

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